EDA News Monday October 20, 2003 From: EDACafe _____ Cadence _____ About This Issue Testing, Testing, 123 ITC, DFT, ATE and so forth _____ October 13 - 17 By Peggy Aycinena Read business product alliance news and analysis of weekly happenings _____ Testing 1 - ITC Revisited ITC 2003 (the International Test Conference) was held this year at the Convention Center in Charlotte, North Carolina, from the 30th of September through the 2nd of October. ITC's organizers describe it as: "The world's premier conference dedicated to the electronic test of devices, boards and systems, covering the complete cycle from design verification, test, diagnosis, failure analysis and back to process and design improvement. At ITC, test and design professionals confront the challenges the industry faces, and learn how these challenges are being addressed by the combined efforts of academia, design tool and equipment suppliers, designers, and test engineers." Given all of this, it's not surprising that a lot of people try to get to ITC each and every year. However, as is still the reality in these challenging days, travel budgets are tight and not everybody who wanted to go to ITC 2003 was able to get there. Tony Ambler was one of the lucky ones who did get to go to Charlotte. But then he was General Chair for ITC 2003, so it was probably a safe bet that, travel budgets notwithstanding, he'd be there. Two weeks after the fact, Ambler sat in his office on the campus of the University of Texas at Austin (where he's Chairman of the Department of Electrical & Computer Engineering) and patiently answered questions about ITC in a phone call from one of those who would have liked to have attended, but couldn't. Per Ambler: "For starters, attendance was something that we did worry about in the current economic situation. But [to our delight], the number of technical attendees was actually the same as last year. It's true that the number of exhibitors was down, but we fully expect that to turn around in the next several years. [Indicative of that], one of the exhibitors from 2002 told us that they're hoping to be able to exhibit once again next year. That's obviously really good news to hear." "This year's technical program was particularly solid. I was talking with Gordon Roberts, Program Chair, and he said we've had a lot less criticism this year. We always hand out questionnaires to the attendees and, of course, you always get gripes whatever you do. Someone's always miserable about something or other, but nonetheless we always listen to the attendees and [feel this year's ITC was particularly successful because] we had a lot less negative comments than in past years." "For one thing, the program size has increased. The number of paper proposals has gone up, and everybody on the Program Committee has been particularly pleased with the quality of the submissions. You tend to find with a conference like ITC - which is sponsored by the IEEE Computer Society Test Technology Technical Council (as well as the Philadelphia Section of IEEE, with support from Mentor Graphics and Advantest) - that people submitting papers are very self-selecting. They usually won't submit a paper if it's not quite ready." "Of course, there's always the danger that the conference will become too academic. We always go to great lengths to be sure that participants on the Program Committee receive a high level of industrial input as well. We never forget that industry people have as many Masters and PhDs as academics." "Most of us believe that ITC's greatest strength is that it's not just Industry, and it's not just Academics. It's a free form dialog taking place between all parties involved and that's exactly what should be happening. We have the leading industrial and academic practitioners all making an impact on ITC, its program, and its future direction." "One problem that we would all admit to is that ITC has tended to drift over the years towards being the International Chip Test Conference, so many of us have [been pushing] to make it a bit more broad-based. We've noticed of late, for instance, that the board test people have been sending a relatively low number of attendees. [Subsequently], the Board Test Action Group, chaired by Ben Bennetts, has made a concerted effort to be sure that board and system test are also included in the program. The keynote this year was given by David Yen, Executive Vice President at Sun Microsystems. He was talking about seeing chip testability through the eyes of a systems person. That [dovetails] with our increased emphasis at ITC on system-level and board-level test." "When I was Program Chair, I tried to do what Ben's Group has now done, but we didn't have the critical mass of bodies then to make a rigorous argument for inclusion. The Board Test Action Group has now guaranteed that there will be space in the program for board and system-level test. And, we've put on extra sessions explicitly for these people, made sure that there are specific tutorial slots in the first few days for system test, that there are panel slots explicitly put aside for board and system test, and three workshops specific to board and system test. The exhibitors have noticed the change and are commenting on it." "[There's another interesting trend in that] you're seeing fewer ATE (automatic test equipment) people at ITC and more EDA exhibitors. Of course, there's a lot of consolidation in the industry - Cadence buying out IBM's testbench stuff (see below) has an impact, for example. But clearly there's a much bigger emphasis these days on DFT (design for test) in the whole test process." "The roadmaps are forecasting that the dramatic increases in device performance mean [traditional test] will not be able to keep up. It's obvious we're going to need to put more testability on the chip. [In conjunction with that], there's been increasing dialog at ITC about moving to low-cost DFT testers. You're still going to need those Big Iron ATE things - and ATE people will still want to sell ATE. But people who didn't want to buy ATE before ITC, are still not wanting to buy ATE even after ITC is over." "I led one of the workshops at ITC ("Future of ATE"). Things weren't quite as focused during the workshop as one would perhaps have wanted. It actually ended up with a lot of arguing to and fro, rather than anyone coming to a final agreement like, 'Yeah, this is how it should go.' [Clearly], the future isn't quite clear as yet." Meanwhile, Charlotte was a new venue for ITC this year and Ambler said the location was chosen "for a variety of reasons, which may or may not have been rational. The decision to hold the conference in Charlotte was made quite a few years ago. Planning has had to take into account our space needs, while the totality of the event - including the panels, talks and exhibits - has outgrown our [traditional] hotel venues. We had to find different locations that could accommodate the program and the exhibits, which caused us to look at more conventions centers. There aren't actually that many around, and given that ITC has traditionally been an East Coast show, we were limited in our choices. We'll be in Charlotte again next year, but the year after that we'll be in Austin." As Ambler lives and works in Austin, it seemed only fair to ask him if he'd exerted undue personal influence on the decision to mount ITC 2005 in his own backyard. He laughed and said, "Austin as a venue was neither suggested nor pushed by myself. The Austin Convention Center is a very nice facility, located in a very pleasant part of town and only a block from 6th Street." Ambler came to Austin himself just seven years ago - "straight from the U.K." - and claims he's never looked back as the weather in Austin is quite good, drier than in the U.K., and the people in Austin are delightful (although he adds the city is a "bit of an oasis" in Texas). I asked him about his own particular area of research: "I'm an academic, but I'm unusual because I have an industrial bias. Also, unlike most faculty working in test, I tend to [gravitate] towards system and field service test. I try to debate whether [a particular technique] offers an economically viable prospect. A [strategy] has to provide more than just high coverage - it has to be demonstrably less expensive than those currently in use." "It's true that some schools [doing research in test] are more interested in pure research. Those schools which are [pursuing] the purely academic issues are right and proper in doing so - the ivory tower should be thinking 20 years out. But you also have to have those academics who balance [that type of research] with industry research that's perhaps just 5 years out. Just as we believe it's appropriate to have both viewpoints represented at ITC." When I suggested that he might be one of those academics who was "wonderfully pragmatic," he said those were exactly the words that I should use in describing him - those and the words, "handsome, suave, and sophisticated." (Unfortunately it was only a phone call, so probably best to maintain a healthy level of skepticism with respect that last bit until independently corroborated.) Meanwhile, it's clear that Ambler's got more than just a simple dollop of British wit and charm on his CV. He's a fellow of the IEEE, author and editor of numerous texts on test economics, served as Program Chair and General Chair for the IEEE International Conference on Computer Design (ICCD), General Chair of the European Design and Test Conference, as well as Program Chair and now General Chair of ITC. He's also on the editorial boards of IEEE Design and Test; and the Journal of Electronic Test, Theory and Application. Maybe the best words are, "Busy guy." Testing 2 - Cadence and IBM Rahul Razdan is Corporate Vice President and General Manager of the Cadence Systems and Functional Verification Group. I spoke to him several weeks ago in conjunction with Cadence's ITC announcement regarding the IBM test tools and technology acquired by Cadence in September 2002 - now being marketed as Cadence Encounter Test Solutions. Prior to Cadence, Razdan served in various capacities at both DEC and IBM, where he worked extensively in ATPG (automatic test pattern generation) technology. His PhD (from Harvard) is in the area of dynamically configurable compute engines. He has more than 20 patents in computer architecture, hardware design and software design. It was interesting to hear what he had to say. "IBM has been the leader in Test forever. In fact, most players have some genesis back to IBM relative to their core products. Cadence [was delighted] to acquire the Test Group from IBM [out of Endicott, NY] last year. Our message at ITC was that we're now announcing the general availability of these products in the market place. "We're calling the one portion of the new product the Encounter Test Design Edition and it's aimed at the design team. It includes ATPG, fault generation, compression, scan insertion - all of which are available from our competitors - but we're offering additional functionality on top of that. It's really unique compared to the general offerings out there." "Additionally, the product is capable of handling designs of over 70 million gates. It's true, currently there are not many designs of that size, but they're definitely beginning to show up. Certainly 30 to 40-million gates is not uncommon today." "We feel that our new product offering is unique in many ways. It can handle delay faults - IDDQ testing has caught this failure mechanism in the past by measuring electrical characteristics of the design and determining leaks. But that mechanism has become increasing ineffective. The baseline environment is too noisy to allow IDDQ to be accurate. Therefore, our ATPG engines are generating tests especially for IDDQ faults. Of course, the number of tests generated ends up being much larger. So there's also a focal point for compression. The [subsequent] loss in granularity can sometimes be a problem, so a cost/benefit analysis allows the designer to choose from a range of compression analysis choices. There's never a free lunch in test!" "Also, traditional fault models used stuck-at fault models. But the actual failure mechanism is more complex than that. You need to understand the whole system - pattern faults have multiple stuck-at faults, link faults, all needing an approximation model. That has been addressed in our new offering as well." "The other portion of our new product is called Encounter Test Manufacturing Edition. It's going after the manufacturing side of the business - the fundamental problem on the manufacturing floor when something's not producing the yield and you need to know why. It's a diagnostic that lets you take the netlist of a design and the failure test vectors, and figure out with some high degree of probability where the failure occurred, irrespective of where the failed test vectors are generated from. The product is aimed at accelerating yield. We feel that by offering that capability, we can now offer a full solution for linking test to design." "We know that DFT is connecting increasingly to the ATE world, and we see ourselves as part of that process. We want to connect with all of the ATE players and believe we're offering the basic 'operating' system that connects the design, manufacturing, and ATE communities. Our strategy is to have design-aware manufacturing and manufacturing-aware design - the whole linkage from scan insertion and BIST (built-in self test) to providing a sufficient notion of a design to allow for fault isolation on the manufacturing floor. And, we'll be linking more and more to OpenAccess from the manufacturing floor." "Prior to our purchase [of the IBM tools], Cadence didn't have much by way of test offerings - it was a 'hole' in our portfolio. This purchase is a good one for Cadence. It's also good for IBM. IBM asked themselves, from an investment point of view, 'How do we get what we want relative to the solutions that we need?' There was an investment angle there that made sense for IBM. Also, they had a completely proprietary solution used extensively as part of their ASIC business, which they knew to be a possible impediment to adoption. Both of the these factors - investment and adoption - led to the Cadence purchase." "Now we're driving the technology from within Cadence, although the collaboration with IBM is still on going. They have the ability to direct, at some level, the R&D within Cadence - the collaboration between the two companies will continue to be very close. Of course, IBM has always had the chance to shop around [for test vendors], but now they're predominantly using the tools out of Cadence. The nature of the solutions that are currently available in the open marketplace are such that they don't really match up to the needs that IBM has or had. I don't expect that situation to change as long as Cadence is on the technical edge." Testing 3 - Zorian honored Virage Logic Corp. announced that Yervant Zorian has been named by EETimes as one of a select group of key individuals who have influenced the course of semiconductor development technology. Zorian is one of 13 so honored. The final list was based on input from the EE Times editorial staff, with Editor-in-Chief Brian Fuller overseeing the process. The Press Release from Virage says, "Zorian is currently Vice President and Chief Scientist at Virage. He pioneered work on embedded test technology and is acknowledged as one of the world's leading experts in the field. Zorian founded and currently chairs the IEEE P1500 Standardization Working Group for embedded core test, and has authored over 200 papers and three books. Previously, Zorian was Chief Technical Adviser at LogicVision, and prior to that a Distinguished Member of Technical Staff at Bell Labs. He is Vice President of the IEEE Computer Society for Technical Activities and Editor-in-Chief Emeritus of IEEE Design & Test of Computers. He received an honorary doctorate from the National Academy of Sciences of Armenia and is a Fellow of the IEEE. Zorian has an MS from the University of Southern California, an MBA from the Wharton School of Business, and a PhD from McGill University." Tony Ambler, General Chair of ITC 2003, said, "Yervant has done a tremendous job in facilitating dialog and encouraging others to participate in the field. He was the person who made the Test Technology Technical Council a leading force in the industry. And, of course, he's played a leading role in the creation and development of standards, in particular IEEE P1500. He's very versatile and gets around to talking to just about everybody on many topics." Zorian is also a gentleman and a scholar. A number of years ago as a new staff member at ISD, I was told that my first Focus Report for the magazine would discuss test. To bring me up to speed, I was sent to talk to Zorian. Not only was Yervant extremely informative, but he was also infinitely polite in answering my many questions. For that courtesy, I continue to be grateful and I congratulate him on his most recent honor. Industry News -- Tools and IP Accelerated Technology, the Embedded Systems Division of Mentor Graphics Corp., announced a new version of the XRAY debugger for Symbian OS, an embedded operating system. The Press Release says, "embedded developers of mobile phone applications will have the most complete target-debugging environment available today for Symbian OS." Symbian develops and licenses Symbian OS, a widely utilized operating system for advanced mobile phones. Agilent Technologies Inc. has introduced its RF Design Environment (RFDE) wireless test benches, which the company says offers system-level wireless signal sources and standards measurements from within Cadence Design System's Virtuoso custom design platform. Per the Press Release: "System-level verification of circuit-level designs is performed late in the development cycle. The frequent use of unconnected tools to perform design verification increases risk and costs, leading to delays in the development cycle. Now, wireless system architects can develop test benches early in the development cycle and export them from Agilent's Advanced Design System (ADS) into RFDE. RFIC designers can then access the test benches from within the Cadence analog and mixed-signal design flow framework to verify their circuit designs before going to manufacturing. In addition, several pre-configured wireless test benches are available as an RFDE option, and provide fully parameterized sources and measurements to help meet today's complex wireless standards such as WLAN, 3GPP and TD-SCDMA." Aldec, Inc. announced the release of Riviera 2003.09. The company says the new version includes a new advanced graphical dataflow (allows designer to explore the connectivity of the simulated design and analyze the dataflow among instances, concurrent statements, signals, nets and registers), toggle coverage viewer (now includes a stand-alone viewer for reading the XML generated reports), and X-Trace (creates a report with information about unknown values in the simulation model). Performance optimizations in the new release have yielded, per Aldec, as much as a 2x improvement for VHDL, Verilog and mixed designs on all supported platforms. Better memory allocation and usage in Riviera has also substantially reduced the amount required during both compilation and simulation. Ansoft Corp. has released Ansoft Designer v1.1, software for the design of high-frequency electronic components, circuits, and systems. The new version includes a Solver on Demand link between Ansoft Designer and Ansoft's HFSS, the company's 3D electromagnetic (EM) design tool. The company says that designers and engineers can now dynamically incorporate the effects of arbitrary 3D structures within their high-frequency electronic simulations, and utilize an "advanced schematic-based design flow while incorporating the effects of high-frequency and high-speed components." Among other enhancements, the new release includes new behavioral noise and variable time-step models for advanced sigma-delta fractional-N PLL simulation, new N-port (S-parameter) import of Ansoft Neutral Files (ANF), new multi-variable interpolation for planar EM sub-circuits, enhanced full-planer structure Solver on Demand, and multiple user-specified data extrapolation types. Cadence Design Systems, Inc. announced that STMicroelectronics' Audio Division used the Encounter digital IC design platform technologies to design ST's 130-nanometer XM Radio digital baseband circuit. The companies also said that STMicroelectronics' design partner Accent used SoC Encounter to meet the original tape-out schedule. Pietro Palella, General Manager for ST's TPA Audio and Automotive Group, is quoted in the Press Release: "The move to smaller nanometer geometries increases the complexity of chip development and requires advanced process technologies. Working with Accent and deploying Cadence SoC Encounter addressed our design needs comprehensively, which meant we could tape out our demanding new circuit on time, despite late changes." Also from Cadence - The company announced what it describes as "the industry's first complete front-to-back advanced IC package and printed circuit board (PCB) design flow to run on Linux as part of its version 15.1 IC packaging and PCB design environment release. For design teams looking for proven alternatives to Windows and Unix platforms, Linux offers a high-performance, low-cost, robust and truly open-source operating system (OS). The Cadence 15.1 software release will deliver an entire Cadence IC packaging and PCB design environment on the Linux OS, providing customers with more options as they determine their optimal EDA IT environment." MIPS Technologies, Inc. announced details of a 32-bit synthesizable core family, derivatives of the recently introduced MIPS32 24K microarchitecture, that the company says will help engineers "quickly achieve their SoC design goals by offering a proven path to silicon through optimized front-to-back end methodologies and industry-standard on-chip interconnects." MIPS also announced a new version of its SOC-it system controller, SOC-it OCP, optimized for the OCP on-chip interconnect technology developed as the native interface for all 24K cores. Per the Press Release: "By coupling the SOC-it OCP with 24K cores, MIPS Technologies delivers dramatic time-to-market reductions to customers by pre-engineering the highest performance common system components." Also from MIPS Technologies - The company has announced the MIPS MT ASE (Application Specific Extension), a new multi-threading extension to its signature architecture. The company says that SoC designers will be able to increase delivered system performance through higher processor efficiency in applications that can take advantage of a multi-tasking approach to SoC design. The Press Release also says, "Dedicated IP (such as DSPs) can be eliminated, lowering system costs by migrating more independent functions onto a single MT enabled MIPS-based core. The MIPS MT ASE is tailored toward silicon companies doing MIPS-based designs, and makes the MIPS32 and MIPS64 architectures the only ones within the embedded industry to offer a full spectrum of solutions for SoC customers." Tony Massimini, CTO of Semico Research, is quoted in the Press Release: "Multithreading squeezes more performance out of the same number of clock cycles to deliver greater processor efficiency. At the same time, companies can reduce die area and, therefore, overall costs and power consumption of their design. The bonus benefit, of course, is that this solution is based on an industry-standard architecture that enables users to tap into broad third-party software support for fast adoption." Synopsys, Inc. announced the general availability of its Milkyway design database C-application programming interface (C-API) for EDA vendors. The company says the C-API gives EDA vendors the ability to deliver their products pre-integrated with Synopsys' Galaxy Design Platform. Per the Press Release: "The Milkyway C-API comprises the function prototypes and linkable libraries that allow a stand-alone program to read and write data in the Milkyway database. The Milkyway C-API has been available to customers for several years. Now, both customers and EDA tool developers can use the Milkyway C-API to directly access Milkyway design data with their application programs instead of working through less efficient file transfer formats." Among others, James Lin, Vice President of Technology Infrastructure Group at National Semiconductor, is in the Press Release: "National has used the C-API for several years to integrate internal and external tools with our Milkyway-based design environment. The release of the C-API through MAP-in to EDA vendors will make it possible for us to acquire commercial tools pre-integrated with Milkyway, and provide a well-supported efficient solution for our internal design flows." Tanner EDA has launched L-Edit/SDL, which the company describes as a schematic-driven layout (SDL) tool for its L-Edit layout and verification software. L-Edit/SDL is available as an add-on package for L-Edit version 10.2. L-Edit/SDL enables IC designers to retain the electrical connectivity information from schematic drawings and systematically display the information in design layouts. The company says it replaces a "traditionally manual and complex process, resulting in reduced layout times and increased design accuracy," and generates layouts corresponding to instances and devices. It enables instances to be created from existing cells, allows T-Cells to generate devices based on their parameters in the SPICE file, and adds highlights to the pins and nodes in order to help navigate the user through the design. L-Edit/SDL also inserts flylines, which indicate which pins and nodes are connected to each other and which update automatically as the designer moves the cells so the designer can optimize the placement while seeing the required connections. L-Edit/SDL also includes ECO (engineering change order) tracking. Magma takes the cheese The PR folks at Magma were either high on caffeine or had a really pent-up need to release news this week. No less than 10 Press Releases came across the wires in the last few days, but who knows? Perhaps there were some that I missed. 1 - Magma Design Automation Inc. announced that the company has reached key milestones in its synthesis roadmap, indicating fast-growing market acceptance and strengthening the company's position in the IC implementation market. Since its release in April of this year, more than 30 new and existing Magma customers have purchased Blast Create 4.0 and six designs have already taped out successfully. 2 - Magma announced that Spike Technologies has joined its MagmaTies partner program. Through this program Spike Technologies gains access to Magma's software, methodologies and training and can serve as a qualified design resource to Magma customers. Spike will support Magma's Blast Create synthesis and physical design solution. 3 - Magma and Veritools announced integration of Veritools' flagship Undertow toolset with Magma's Blast Create synthesis solution. Blast Create and Undertow users now have a seamless RTL-to-placed-gates design flow that includes cross-probing and interactive debugging capabilities for very large and complex SoC designs. The combination of Magma and Veritools technology allows designers to find errors in the design intent within the RTL code or timing constraints using familiar techniques such as cross-probing HDL source code, gate-level schematics, block diagrams, state machine diagrams and waveforms. 4 - Magma announced that Chrontel, Inc. has successfully completed the design of a digital visual interface (DVI) chip using Magma's RTL-to-GDSII design system. The DVI transmitter is a display controller that accepts a digital graphics input signal and then up-scales, encodes and transmits the data through a DVI link. The mixed-signal chip, which operates at up to 200 MHz, was designed using Blast Create and Blast Fusion. 5 - Magma announced that Infrant Technologies and NEC Electronics America have taped out a 250 MHz, 3-million-gate network storage device using Magma's integrated RTL-to-GDSII system. Infrant Technologies performed RTL synthesis with Blast Create using a flat design methodology and then handed off the design to NEC Electronics America for physical implementation using Blast Fusion. The design was fabricated in the CB-12M 0.15-micron process technology. With Magma's software, Infrant and NEC Electronics America were able to tape out the device with zero layout-to-synthesis iterations, completing the design in just three months. 6 - Magma announced that Fastrack Design Inc. has delivered a turnkey design exclusively using Magma's RTL-to-GDS flow. 7 - Magma announced that QuantumThink Group Inc. has adopted the Blast Create synthesis solution. QThink now offers customers expertise in Magma's complete RTL-to-GDSII flow. 8 - Magma announced that Broadcom Corp. has taped out a 15-million-gate design using Blast RTL and Blast Fusion. Magma's integrated RTL-to-GDSII system was used to synthesize the largest and most complex block of the design. The companies report that using a single Blast RTL license, performance goals were met and significantly faster total turnaround time was achieved. Blast Fusion was used to implement the entire design. 9 - Magma and NEC Electronics America announced that NEC will accept ASIC design data from Blast Create. The companies say that designs completed for NEC's ASIC customers have shown the hand-off from Magma provides a smooth data transfer and predictable timing closure without the need to iterate from layout back to synthesis. Conventional approaches to logic design require partitioning and delay budgeting of the design into blocks with fewer than 250,000 gates. For today's 10-million-gate and larger SoC designs, this requires many blocks to be integrated at the top level, making chip-level timing convergence unpredictable and causing layout-to-synthesis iterations. Blast Create's capacity, which Magma says is an order of magnitude greater than that of conventional synthesis tools, is reported as giving front-end designers the same advantages that back-end designers have enjoyed - improvements in area, performance and power of 5 percent to 15 percent. 10 - Magma announced that the company's PALACE physical synthesis software now supports Actel's reprogrammable, flash-based ProASIC Plus FPGA device families. Magma says that PALACE unifies logic synthesis and physical design and provides an efficient physical synthesis engine for FPGAs that includes constraint-driven optimization, architecture-specific mapping, and unique support for multi-cycle on-chip communication. The companies says that the support is the result of a 7-month-long, close collaboration between Actel and Aplus Design Technologies, Inc., which was acquired by Magma in July 2003. Coming soon to a theater near you Verify2003 Seminar Series - Sponsored by Axis Systems, CoWare, Denali Software, Novas Software, Sun Microsystems, and Verisity Design, organizers describe these events as "free one-day educational seminars offering a comprehensive review of the latest methodologies, language standards and best-of-breed electronic design automation tools required to verify and debug complex integrated circuits and system-on-chip designs." The event's already underway and has moved from Austin to San Jose and San Diego so far. You can still catch it, however, on October 21st in Munich, Germany, October 28th in Boston, October 30th in Ottawa, or November 4th in Santa Clara. ( www.verifyseminars.com ) In the category of ... This one's for Sheryl In May 1998, my father was diagnosed with bladder cancer after having ignored symptoms for over a year. He was 75, a doctor, and should have known better. He was treated throughout the summer of 1998 with BCG, but that failed, so he had his bladder and prostate removed in September 1998. He was fitted with an ostomy bag and my mother became his tireless ostomy nurse. He also began 6 months of chemotherapy and started wearing a hat both night and day. Sometimes his bag leaked, which caused him no end of humiliation. He often left a dinner party suddenly and without explanation. In February 1999, my brother - then 49 - was diagnosed with prostate cancer. His cancer was discovered by way of his PSA level during his regular annual check-up. As prostate cancer is not considered urgent, the surgeon - who was the same surgeon that had operated on my father - was not able to operate on my brother until April. While my brother was in surgery in April 1999, his wife, my mother, my father, my husband, and my sister all waited in the waiting room. My father still didn't have any hair and had started wearing suspenders because he couldn't get a belt to work around the ostomy bag. When the surgery was over, the surgeon reported out that all had gone well. He was a young doctor, with steady hands, and my brother was his first surgery of the day. The surgeon was appropriately confident of the results of his handwork. My brother recovered (after several months) and did not have to have radiation or chemo. The afternoon of my brother's surgery that April, my sister left the hospital and went straight to an appointment with her own surgeon. She had been to see her internist the day before and he had been alarmed by a lump in her breast. She would have seen the surgeon the very next morning, but she wanted to be at the hospital with my family during my brother's surgery. My sister had actually noticed a suspicious lump 4 months earlier, but had been told at that time by a doctor who was not her regular primary care physician that she was a "hypochondriac." My sister was a public health nurse and administrator. She should have known better. As you've probably already guessed, the afternoon of April 16, 1999, my sister was diagnosed with advanced stage breast cancer. She was 51. She called me that night with the news and asked me to tell Mom and Dad. She didn't have the strength to face them after all that they had already been through that day and over the previous year. Exactly 6 months later my sister died - on October 16, 1999 - but not before enduring a lumpectomy, a mastectomy, liver surgery, gall bladder surgery, a collapsed lung during surgery to implant a chemo-port, and 5 months of adriamysin. She left a husband of 30 years, one high school senior, and one college senior. In March 2001, my father was diagnosed with liver cancer. He died 4 weeks later, 18 months to the day after my sister. Now you may think it's macabre to keep track of these days, these months, these coincidences, but what are you going to do when they're stuck in your head? In any case, today is October 16th again. My sister has been gone 4 years today. She did not get to see her younger son graduate from high school, nor her older son graduate from college. Neither will she see that same son marry next week in South Carolina, although the rest of the clan will certainly be there - hankies in hand. The clan was also on hand en masse last month to see my late sister's husband remarry. There were lots of hankies at that wedding as well, as you can imagine. Life goes on. When I'm done here, I'm going to go watch Martinez face down Clemens and pray that there's some small shred of justice left in the trembling Baseball ether. I'm not going to think about Dusty Baker. I'm not going to think about sorrow and loss. I'm going to believe, as my sister and my father did, that every day is a good day - as long as you're breathing and able to look with loving eyes on the people around you that really count. You? I hope you're on the phone right now. I hope you're scheduling your annual exam. Get your breast exam. Bear up. Endure the mammogram. Or don't - if you are worried about conflicting reports from the medical community about its efficacy - but at least see your doctor once a year. Don't smoke. Get your prostate exam. Bear up. Endure it. Get your PSA level checked. Don't smoke. If you're over 50, get your colonoscopy. Bear up. Endure it. How bad can it be? Don't smoke. And ask not for whom the bell tolls Who the hell knows For whom the bell tolls --Peggy Aycinena is a Contributing Editor and can be reached by clicking here . You are subscribed as: [dolinsky@gsu.by]. CafeNews is a service for EDA professionals. EDACafe respects your online time and Internet privacy. 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